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| Datasheet File OCR Text: |
| 8 bit microcontroller tlcs-870/c series TMP86FS28FG
the information contained herein is subject to change without notice. 021023_d toshiba is continually working to improve the qua lity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utiliz ing toshiba products, to comply with the standards of safety in making a safe design for the entire sy stem, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most r ecent toshiba products specifications. also, please keep in mind the precauti ons and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, of fice equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation in struments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohib ited under any applicable laws and regulations. 060106_q the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infring ements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliabil ity assurance/handling precautions. 030619_s ? 2007 toshiba corporation all rights reserved revision history date revision 2006/2/9 tentative 1 first release 2006/3/6 tentative 2 first release 2006/4/13 1 first release 2006/6/29 2 periodical updating.no change in contents. 2006/9/28 3 contents revised 2007/7/23 4 contents revised i table of contents TMP86FS28FG 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. operational description 2.1 cpu core functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 memory address map ............................................................................................................................... 9 2.1.2 program memory (flash) .......................................................................................................................... 9 2.1.3 data memory (ram) ............................................................................................................................... .. 9 2.2 system clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 clock generator ............................................................................................................................... ....... 10 2.2.2 timing generator ............................................................................................................................... ..... 12 2.2.2.1 configuration of timing generator 2.2.2.2 machine cycle 2.2.3 operation mode control circuit .............................................................................................................. 13 2.2.3.1 single-clock mode 2.2.3.2 dual-clock mode 2.2.3.3 stop mode 2.2.4 operating mode control ......................................................................................................................... 18 2.2.4.1 stop mode 2.2.4.2 idle1/2 mode and sleep1/2 mode 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) 2.2.4.4 slow mode 2.3 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.1 external reset input ............................................................................................................................... 31 2.3.2 address trap reset ............................................................................................................................... ... 32 2.3.3 watchdog timer reset .............................................................................................................................. 32 2.3.4 system clock reset ............................................................................................................................... ... 32 3. interrupt control circuit 3.1 interrupt latches (il29 to il2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.1 interrupt master enable flag (imf) .......................................................................................................... 36 3.2.2 individual interrupt enable flags (ef29 to ef4) ...................................................................................... 37 note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 interrupt acceptance processing is packaged as follows. ....................................................................... 39 3.3.2 saving/restoring general-purpose registers ............................................................................................ 40 3.3.2.1 using push and pop instructions 3.3.2.2 using data transfer instructions 3.3.3 interrupt return ............................................................................................................................... ......... 41 3.4 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.1 address error detection .......................................................................................................................... 42 3.4.2 debugging ............................................................................................................................... ............... 42 ii 3.5 undefined instruction interrupt (intundef) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6 address trap interrupt (intatrap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.7 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4. special function r egister (sfr) 4.1 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 dbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5. i/o ports 5.1 port p0 (p00 to p02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.2 port p1 (p10 to p17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3 port p2 (p20 to p22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.4 port p3 (p30 to p37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.5 port p4 (p40 to p47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.6 port p5 (p50 to p57) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.7 port p6 (p60 to p67) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.8 port p7 (p70 to p77) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.9 port p8 (p80 to p87) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6. watchdog timer (wdt) 6.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.2 watchdog timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.2.1 malfunction detection methods using the watchdog timer ................................................................... 72 6.2.2 watchdog timer enable ......................................................................................................................... 73 6.2.3 watchdog timer disable ........................................................................................................................ 74 6.2.4 watchdog timer interrupt (intwdt) ...................................................................................................... 74 6.2.5 watchdog timer reset ........................................................................................................................... 75 6.3 address trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.1 selection of address trap in internal ram (atas) ................................................................................ 76 6.3.2 selection of operation at address trap (atout) .................................................................................. 76 6.3.3 address trap interrupt (intatrap) ....................................................................................................... 76 6.3.4 address trap reset ............................................................................................................................... . 77 7. time base timer (tbt) 7.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.1.1 configuration ............................................................................................................................... ........... 79 7.1.2 control ............................................................................................................................... ..................... 79 7.1.3 function ............................................................................................................................... ................... 80 7.2 divider output (dvo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.2.1 configuration ............................................................................................................................... ........... 81 7.2.2 control ............................................................................................................................... ..................... 81 8. 16-bit timercoun ter (tc10,tc11) 8.1 16-bit timercounter 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 iii 8.1.1 configuration ............................................................................................................................... ........... 83 8.1.2 timercounter control ............................................................................................................................. 8 4 8.1.3 function ............................................................................................................................... ................... 85 8.1.3.1 timer mode 8.1.3.2 external trigger timer mode 8.1.3.3 event counter mode 8.1.3.4 window mode 8.1.3.5 pulse width measurement mode 8.1.3.6 programmable pulse generate (ppg) output mode 8.2 16-bit timercounter 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.2.1 configuration ............................................................................................................................... ........... 97 8.2.2 timercounter control ............................................................................................................................. 9 8 8.2.3 function ............................................................................................................................... ................... 99 8.2.3.1 timer mode 8.2.3.2 external trigger timer mode 8.2.3.3 event counter mode 8.2.3.4 window mode 8.2.3.5 pulse width measurement mode 8.2.3.6 programmable pulse generate (ppg) output mode 9. 8-bit timercounter (tc3, tc4) 9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.1 8-bit timer mode (tc3 and 4) .............................................................................................................. 117 9.3.2 8-bit event counter mode (tc3, 4) ...................................................................................................... 118 9.3.3 8-bit programmable divider ou tput (pdo) mode (tc3, 4) ................................................................... 118 9.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4) ................................................................ 121 9.3.5 16-bit timer mode (tc3 and 4) ............................................................................................................ 123 9.3.6 16-bit event counter mode (tc3 and 4) .............................................................................................. 124 9.3.7 16-bit pulse width modulation (pwm) output mode (tc3 and 4) ........................................................ 124 9.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4) ............................................. 127 9.3.9 warm-up counter mode ....................................................................................................................... 129 9.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) 9.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 10. 8-bit timercounter (tc5, tc6) 10.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 10.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.3.1 8-bit timer mode (tc5 and 6) ............................................................................................................ 137 10.3.2 8-bit event counter mode (tc5, 6) .................................................................................................... 138 10.3.3 8-bit programmable divider output (pdo) mode (tc5, 6) ................................................................. 138 10.3.4 8-bit pulse width modulation (pwm) output mode (tc5, 6) .............................................................. 141 10.3.5 16-bit timer mode (tc5 and 6) .......................................................................................................... 143 10.3.6 16-bit event counter mode (tc5 and 6) ............................................................................................ 144 10.3.7 16-bit pulse width modulation (pwm) output mode (tc5 and 6) ...................................................... 144 10.3.8 16-bit programmable pulse generate (ppg) output mode (tc5 and 6) ........................................... 147 10.3.9 warm-up counter mode ..................................................................................................................... 149 10.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) 10.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 11. synchronous serial interface (sio) 11.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 iv 11.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.3.1 clock source ............................................................................................................................... ........ 153 11.3.1.1 internal clock 11.3.1.2 external clock 11.3.2 shift edge ............................................................................................................................... ............. 155 11.3.2.1 leading edge 11.3.2.2 trailing edge 11.4 number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.5 number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.6 transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.6.1 4-bit and 8-bit transfer modes ............................................................................................................. 156 11.6.2 4-bit and 8-bit receive modes ............................................................................................................. 158 11.6.3 8-bit transfer / receive mode ............................................................................................................... 159 12. asynchronous serial interface (uart1 ) 12.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.8.1 data transmit operation .................................................................................................................... 166 12.8.2 data receive operation ..................................................................................................................... 166 12.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12.9.1 parity error ............................................................................................................................... ........... 167 12.9.2 framing error ............................................................................................................................... ....... 167 12.9.3 overrun error ............................................................................................................................... ....... 167 12.9.4 receive data buffer full ..................................................................................................................... 168 12.9.5 transmit data buffer empty ............................................................................................................... 168 12.9.6 transmit end flag .............................................................................................................................. 169 13. asynchronous serial interface (uart0 ) 13.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.8.1 data transmit operation .................................................................................................................... 176 13.8.2 data receive operation ..................................................................................................................... 176 13.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13.9.1 parity error ............................................................................................................................... ........... 177 13.9.2 framing error ............................................................................................................................... ....... 177 13.9.3 overrun error ............................................................................................................................... ....... 177 13.9.4 receive data buffer full ..................................................................................................................... 178 13.9.5 transmit data buffer empty ............................................................................................................... 178 13.9.6 transmit end flag .............................................................................................................................. 179 v 14. 10-bit ad converter (adc) 14.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.2 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 14.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 14.3.1 software start mode ........................................................................................................................... 185 14.3.2 repeat mode ............................................................................................................................... ....... 185 14.3.3 register setting ............................................................................................................................... . 186 14.4 stop/slow modes during ad conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 14.5 analog input voltage and ad conversion result . . . . . . . . . . . . . . . . . . . . . . . 188 14.6 precautions about ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 14.6.1 analog input pin voltage range ........................................................................................................... 189 14.6.2 analog input shared pins .................................................................................................................... 189 14.6.3 noise countermeasure ....................................................................................................................... 189 15. key-on wakeup (kwu) 15.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16. lcd driver 16.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 16.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 16.2.1 lcd driving methods .......................................................................................................................... 195 16.2.2 frame frequency ............................................................................................................................... .. 196 16.2.3 driving method for lcd driver ............................................................................................................ 197 16.2.3.1 when using the booster circuit (lcdcr vi 17.4.1 flash memory control in the serial prom mode ............................................................................... 215 17.4.2 flash memory control in the mcu mode ............................................................................................ 216 17.4.2.1 how to write to the flash memory by executing a user write control program in the ram area (in the mcu mode) 18. serial prom mode 18.1 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 18.2 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 18.3 serial prom mode setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 18.3.1 serial prom mode control pins ........................................................................................................ 220 18.3.2 pin function ............................................................................................................................... ......... 220 18.3.3 example connection for on-board writing ......................................................................................... 221 18.3.4 activating the serial prom mode ...................................................................................................... 222 18.4 interface specifications for uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 18.5 operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.6 operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.6.1 flash memory erasing mode (operating command: f0h) ................................................................. 226 18.6.2 flash memory writing mode (operation command: 30h) .................................................................. 228 18.6.3 flash memory sum output mode (operation command: 90h) ......................................................... 231 18.6.4 product id code output mode (operation command: c0h) .............................................................. 232 18.6.5 flash memory status output mode (operation command: c3h) ...................................................... 234 18.6.6 flash memory read protection setting mode (operation command: fah) ...................................... 235 18.7 error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 18.8 checksum (sum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 18.8.1 calculation method ............................................................................................................................. 2 37 18.8.2 calculation data ............................................................................................................................... ... 238 18.9 intel hex format (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 18.10 passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 18.10.1 password string ............................................................................................................................... . 240 18.10.2 handling of password error .............................................................................................................. 240 18.10.3 password management during program development .................................................................... 240 18.11 product id code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 18.12 flash memory status code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 18.13 specifying the erasure area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 18.14 flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 18.15 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 19. input/output circuitry 19.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 19.2 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 20. electrical characteristics 20.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 20.2 operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 20.2.1 mcu mode (flash programming or erasing) ..................................................................................... 250 20.2.2 mcu mode (except flash progra mming or erasing) ......................................................................... 250 20.2.3 serial prom mode ............................................................................................................................. 2 51 20.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 20.4 ad conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 20.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 20.6 flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 vii 20.7 recommended oscillating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 20.8 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 21. package dimensions this is a technical docu ment that describes the operat ing functions and electrical specifications of the 8-bit microc ontroller series tlcs-870/c (lsi). viii page 1 TMP86FS28FG cmos 8-bit microcontroller ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reli ability of its products. neverthel ess, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vul nerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, pleas e ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba se miconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or re liability or a malfunctionor failure of which may cause loss of human life or bod ily injury (?unintended usage?). unintended us age include atomic energy control instru ments, airplane or spaceship instruments, transporta tion instruments, traffic signal instrume nts, combustion control instruments, medi cal instru- ments, all types of safety dev ices, etc. unintended usage of toshiba products li sted in this document shall be made at the cust omer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and /or sale are prohibited under any appl icable laws and regulations. 060106_q ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patent s or other rights of toshiba or the third parties. 070122_c ? the products described in this document are subjec t to foreign exchange and foreign trade control laws. 060925_e ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/h andling precautions. 030619_s this product uses the super flash ? technology under the licence of silicon storage technology, inc. super flash ? is registered trademark of silicon storage technology, inc. TMP86FS28FG the TMP86FS28FG is a single-chip 8-bit high-speed a nd high-functionality microcomputer incorporating 61440 bytes of flash memory. it is pin-compatible with the tmp86cs28fg (mask rom version). the TMP86FS28FG can realize operations equivalent to those of the tmp86cs28fg by programming the on-chip flash memory. 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 0.25 s (at 16 mhz) 122 s (at 32.768 khz) - 132 types & 731 basic instructions 2. 23interrupt sources (external : 6 internal : 17) 3. input / output ports (62 pins) 4. watchdog timer 5. prescaler - time base timer - divider output function 6. 16-bit timer counter: 2 ch - timer, external trigger, wi ndow, pulse width measurement, event counter, programmable pulse generate (ppg) modes 7. 8-bit timer counter : 4 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg) modes product no. rom (flash) ram package mask rom mcu emulation chip TMP86FS28FG 61440 bytes 2048 bytes qfp80-p-1420-0.80b tmp86cs28fg tmp86c989xb page 2 1.1 features TMP86FS28FG 8. 8-bit uart/sio: 1 ch 9. 8-bit uart : 1 ch 10. 10-bit successive approximation type ad converter - analog input: 8 ch 11. key-on wakeup : 4 ch 12. lcd driver/controller built-in voltage booster for lcd driver with display memory lcd direct drive capability (max 40 seg u 4 com) 1/4,1/3,1/2duties or static drive are programmably selectable 13. clock operation single clock mode dual clock mode 14. low power consumption operation stop mode: oscillation stops. (battery/capacitor back-up.) slow1 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock stop.) slow2 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock oscillate.) idle0 mode: cpu stops, and only the time-based-tim er(tbt) on peripherals operate using high fre- quency clock. release by falling edge of th e source clock which is set by tbtcr page 3 TMP86FS28FG 1.2 pin assignment figure 1-1 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 vss xout test vdd (xtin) p21 (xtout) p22 reset ( int5 / stop ) p20 p00 (int3/ ppg10 ) p02 varef avdd (ain0) p10 (ain1) p11 (stop2/ain2) p12 (stop3/ain3) p13 (stop4/ain4) p14 (stop5/ain5) p15 (ain6) p16 ( int0 ) p30 avss p31( dvo ) p33 p34(so/rxd1) p36( sck ) p35(si/txd1) p50 (seg31/txd0) p47 (seg32) p46 (seg33) p45 (seg34) p44 (seg35) p43 (seg36/tc11) p42 (seg37/ ppg11 ) p41 (seg38/int2) p40 (seg39/int1) p37 (tc10/int4) p32 p62 (seg21) p61 (seg22) p60 (seg23) p57 (seg24) p56 (seg25) p55 (seg26/tc6/ pdo6/pwm6/ppg6 ) p54 (seg27/tc5/ pdo5/pwm5 ) p53 (seg28/tc4/ pdo4/pwm4/ppg4 ) p52 (seg29/tc3/ pdo3/pwm3 ) p51 (seg30/rxd0) p75 (seg10) p80 (seg7) p77 (seg8) p76 (seg9) p74 (seg11) p73 (seg12) p72 (seg13) p71 (seg14) p70 (seg15) p67 (seg16) p66 (seg17) p65 (seg18) p64 (seg19) p63 (seg20) (ain7) p17 p01 xin (seg6) p81 (seg5) p82 (seg4) p83 (seg3) p84 (seg1) p86 (seg0) p87 com3 com2 com1 com0 v3 v2 v1 c1 c0 (seg2) p85 page 4 1.3 block diagram TMP86FS28FG 1.3 block diagram figure 1-2 block diagram page 5 TMP86FS28FG 1.4 pin names and functions the TMP86FS28FG has mcu mode, parallel prom mode , and serial prom mode. table 1-1 shows the pin functions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/4) pin name pin number input/output functions p02 ppg10 int3 12 io o i port02 ppg10 output external interrupt 3 input p01 11 io port01 p00 10 io port00 p17 ain7 22 io i port17 analog input7 p16 ain6 21 io i port16 analog input6 p15 ain5 stop5 20 io i i port15 analog input5 stop5 input p14 ain4 stop4 19 io i i port14 analog input4 stop4 input p13 ain3 stop3 18 io i i port13 analog input3 stop3 input p12 ain2 stop2 17 io i i port12 analog input2 stop2 input p11 ain1 16 io i port11 analog input1 p10 ain0 15 io i port10 analog input0 p22 xtout 7 io o port22 resonator connecting pins(32.768 khz) for inputting external clock p21 xtin 6 io i port21 resonator connecting pins(32.768 khz) for inputting external clock p20 stop int5 9 io i i port20 stop mode release signal input external interrupt 5 input p37 tc10 int4 31 io i i port37 tc10 input external interrupt 4 input p36 sck 30 io io port36 serial clock i/o p35 si txd1 29 io i o port35 serial data input uart data output 1 p34 so rxd1 28 io o i port34 serial data output uart data input 1 page 6 1.4 pin names and functions TMP86FS28FG p33 27 io port33 p32 26 io port32 p31 dvo 25 io o port31 divider output p30 int0 24 io i port30 external interrupt 0 input p47 seg32 39 io o port47 lcd segment output 32 p46 seg33 38 io o port46 lcd segment output 33 p45 seg34 37 io o port45 lcd segment output 34 p44 seg35 36 io o port44 lcd segment output 35 p43 seg36 tc11 35 io o i port43 lcd segment output 36 tc11 input p42 seg37 ppg11 34 io o o port42 lcd segment output 37 ppg11 output p41 seg38 int2 33 io o i port41 lcd segment output 38 external interrupt 2 input p40 seg39 int1 32 io o i port40 lcd segment output 39 external interrupt 1 input p57 seg24 47 io o port57 lcd segment output 24 p56 seg25 46 io o port56 lcd segment output 25 p55 seg26 tc6 pdo6/pwm6/ppg6 45 io o i o port55 lcd segment output 26 tc6 input pdo6/pwm6/ppg6 output p54 seg27 tc5 pdo5/pwm5 44 io o i o port54 lcd segment output 27 tc5 input pdo5/pwm5 output p53 seg28 tc4 pdo4/pwm4/ppg4 43 io o i o port53 lcd segment output 28 tc4 input pdo4/pwm4/ppg4 output p52 seg29 tc3 pdo3/pwm3 42 io o i o port52 lcd segment output 29 tc3 input p51 seg30 rxd0 41 io o i port51 lcd segment output 30 uart data input 0 table 1-1 pin names and functions(2/4) pin name pin number input/output functions page 7 TMP86FS28FG p50 seg31 txd0 40 io o o port50 lcd segment output 31 uart data output 0 p67 seg16 55 io o port67 lcd segment output 16 p66 seg17 54 io o port66 lcd segment output 17 p65 seg18 53 io o port65 lcd segment output 18 p64 seg19 52 io o port64 lcd segment output 19 p63 seg20 51 io o port63 lcd segment output 20 p62 seg21 50 io o port62 lcd segment output 21 p61 seg22 49 io o port61 lcd segment output 22 p60 seg23 48 io o port60 lcd segment output 23 p77 seg8 63 io o port77 lcd segment output 8 p76 seg9 62 io o port76 lcd segment output 9 p75 seg10 61 io o port75 lcd segment output 10 p74 seg11 60 io o port74 lcd segment output 11 p73 seg12 59 io o port73 lcd segment output 12 p72 seg13 58 io o port72 lcd segment output 13 p71 seg14 57 io o port71 lcd segment output 14 p70 seg15 56 io o port70 lcd segment output 15 p87 seg0 71 io o port87 lcd segment output 0 p86 seg1 70 io o port86 lcd segment output 1 p85 seg2 69 io o port85 lcd segment output 2 p84 seg3 68 io o port84 lcd segment output 3 p83 seg4 67 io o port83 lcd segment output 4 p82 seg5 66 io o port82 lcd segment output 5 table 1-1 pin names and functions(3/4) pin name pin number input/output functions page 8 1.4 pin names and functions TMP86FS28FG p81 seg6 65 io o port81 lcd segment output 6 p80 seg7 64 io o port80 lcd segment output 7 com3 72 o lcd common output 3 com2 73 o lcd common output 2 com1 74 o lcd common output 1 com0 75 o lcd common output 0 v3 76 i lcd voltage booster pin v2 77 i lcd voltage booster pin v1 78 i lcd voltage booster pin c1 79 i lcd voltage booster pin c0 80 i lcd voltage booster pin xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test. normally, be fixed to low. varef 14 i analog base voltage input pin for a/d conversion avdd 13 i analog power supply avss 23 i analog power supply vdd 5 i +5v vss 1 i 0(gnd) table 1-1 pin names and functions(4/4) pin name pin number input/output functions page 9 TMP86FS28FG 2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system cl ock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86FS28FG memory is composed flash, ram, dbr(data buffer register) and sfr(special func- tion register). they are all mapped in 64-kbyte address space. figure 2-1 shows the TMP86FS28FG figure 2-1 memory address map 2.1.2 program memory (flash) the TMP86FS28FG has a 61440 bytes (address 1000h to ffffh) of program memory (flash ). 2.1.3 data memory (ram) the TMP86FS28FG has 2048 bytes (address 0040h to 083fh) of internal ram. the first 192 bytes (0040h to 00ffh) of the internal ra m are located in the direct area; inst ructions with shorten operations are available against such an area. sfr 0000 h 64 bytes sfr: ram: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word random access memory includes: data memory stack 003f h ram 0040 h 2048 bytes 083f h dbr 0f00 h 256 bytes dbr: data buffer register includes: peripheral control registers peripheral status registers lcd display memory 0fff h 1000 h flash: program memory flash 61440 bytes ffa0 h vector table for interrupts (32 bytes) ffbf h ffc0 h vector table for vector call instructions (32 bytes) ffdf h ffe0 h vector table for interrupts (32 bytes) ffff h page 10 2. operational description 2.2 system clock controller TMP86FS28FG the data memory contents become un stable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 2-2 syst em colck control 2.2.1 clock generator the clock generator generates the basic clock which pr ovides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation ci rcuits: one for the high-frequency clock and one for the low-frequency clock. power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. the high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the xin/xout and xtin/xtout pins respectively. clock input from an exte rnal oscillator is also possible. in this case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. example :clears ram to ?00h?. (TMP86FS28FG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 07ffh sramclr: ld (hl), a inc hl dec bc jrs f, sramclr tbtcr syscr2 syscr1 xin xout xtin xtout fc 0036 h 0038 h 0039 h fs timing generator control register timing generator standby controller system clocks clock generator control high-frequency clock oscillator low-frequency clock oscillator clock generator system control registers page 11 TMP86FS28FG figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscilla tion frequency should create the program for the adjust- ment in advance. xout xin (open) xout xin xtout xtin (open) xtout xtin (a) crystal/ceramic resonator (b) external oscillator (c) crystal (d) external oscillator high-frequency clock low-frequency clock page 12 2. operational description 2.2 system clock controller TMP86FS28FG 2.2.2 timing generator the timing generator generates the various system cloc ks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo ) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 7. lcd 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, syscr2 page 13 TMP86FS28FG note 1: in single clock mode, do not set dv7ck to ?1?. note 2: do not set ?1? on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal1/2 mode, the dv 7ck setting is ineffective during the warm-up period after release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 machine cycle instruction execution and peripheral hardware operat ion are synchronized with the main system clock. the minimum instruction execution uni t is called an ?machine cycle?. th ere are a total of 10 different types of instructions for the tlcs-870/c series: ra nging from 1-cycle instructions which require one machine cycle for execution to 10-cyc le instructions which require 10 machine cycles fo r execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops th e oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock. there are three operating modes: single clock mode, dual clock mode and stop mode. these modes are cont rolled by the system cont rol registers (syscr1 and syscr2). figure 2-6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode only the oscillation circuit for the high-frequenc y clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports . the main-system clock is obtained from the high-frequency clock. in the single-clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip pe ripherals operate using the high-frequency clock. the TMP86FS28FG is placed in this mode after reset. timing generator control register tbtcr (0036h) 76543210 (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 1/fc or 1/fs [s] page 14 2. operational description 2.2 system clock controller TMP86FS28FG (2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2 page 15 TMP86FS28FG switching back and forth between slow1 and slow2 modes are performed by syscr2 page 16 2. operational description 2.2 system clock controller TMP86FS28FG note 1: normal1 and normal2 modes are generically called no rmal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2: the mode is released by fa lling edge of tbtcr page 17 TMP86FS28FG note 1: always set retm to ?0? when transiting from normal mode to stop mode. always set retm to ?1? when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *; don?t care note 4: bits 1 and 0 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = ?0?, input value is fixed to ?0?; therefore it may cause external interrupt request on account of falling edge. note 6: when the key-on wakeup is used, relm should be set to "1". note 7: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 8: the warmig-up time should be set correctly for using oscillator. note 1: a reset is applied if both xen and xten are cleared to ?0?, xen is cleared to ?0? when sysck = ?0?, or xten is cleared to ?0? when sysck = ?1?. note 2: *: don?t care, tg: timing generator, *; don?t care note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to ?1? simultaneously. note 5: because returning from idle0/sleep0 to normal1/slow 1 is executed by the asynchronous internal clock, the period of idle0/sleep0 mode might be shorter than the period setting by tbtcr page 18 2. operational description 2.2 system clock controller TMP86FS28FG 2.2.4 operating mode control 2.2.4.1 stop mode stop mode is controlled by the system control register 1, the stop pin input and key-on wakeup input (stop5 to stop2) which is controlled by the stop mode release control register (stopcr). the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting syscr1 page 19 TMP86FS28FG figure 2-7 level-s ensitive release mode note 1: even if the stop pin input is low after warm-up start, the stop mode is not restarted. note 2: in this case of changing to the level-s ensitive mode from the edge-s ensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = ?0?) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short pr ogram is executed repeat edly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. do not use any stop5 to stop2 pin input for releasing stop mode in edge-sensitive release mode. figure 2-8 edge-sensitive release mode example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf m 0 set (syscr1). 7 ; starts stop mode sint5: reti example :starting stop mode from normal mode di ; imf m 0 ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation normal operation normal operation v ih stop mode is released by the hardware at the rising edge of stop pin input. warm up stop mode started by the program. stop operation stop operation stop pin xout pin page 20 2. operational description 2.2 system clock controller TMP86FS28FG stop mode is released by the following sequence. 1. in the dual-clock mode, when returning to normal2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to slow1 mode, only the low- frequency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all internal operations remain halted. four differ ent warm-up times can be selected with the syscr1 page 21 TMP86FS28FG figure 2-9 stop mode start/release instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock page 22 2. operational description 2.2 system clock controller TMP86FS28FG 2.2.4.2 idle1/2 mode and sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during these modes. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. the program counter holds the address 2 ahead of th e instruction which starts these modes. figure 2-10 idle1/ 2 and sleep1/2 modes reset reset input ?0? ?1? (interrupt release mode) yes no no cpu and wdt are halted interrupt request imf interrupt processing normal release mode yes starting idle1/2 and sleep1/2 modes by instruction execution of the instruc- tion which follows the idle1/2 and sleep1/2 modes start instruction page 23 TMP86FS28FG ? start the idle1/2 and sleep1/2 modes after imf is set to "0", set the individual inte rrupt enable flag (ef) which releases idle1/2 and sleep1/2 modes. to start idle1/2 and sl eep1/2 modes, set syscr2 page 24 2. operational description 2.2 system clock controller TMP86FS28FG figure 2-11 idle1/2 and sleep1/2 modes start/release halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 operate operate operate acceptance of interrupt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (a) idle1/2 and sleep1/2 modes start (example: star ting with the set instruction located at address a) (b) idle1/2 and sleep1/2 modes release page 25 TMP86FS28FG 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following stat us is maintained during idle0 and sleep0 modes. 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 and sleep0 modes were entered. 3. the program counter holds the address 2 ahead of the instru ction which starts idle0 and sleep0 modes. note: before starting idle0 or sleep0 mode, be sure to stop (disable) peripherals. figure 2-12 idle 0 and sleep0 modes yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted reset tbt source clock falling edge tbtcr page 26 2. operational description 2.2 system clock controller TMP86FS28FG ? start the idle0 and sleep0 modes stop (disable) peripherals such as a timer counter. to start idle0 and sleep0 modes, set syscr2 page 27 TMP86FS28FG figure 2-13 idle0 and slee p0 modes start/release halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) idle0 and sleep0 modes start (example: starting with the set instruction located at address a (b) idle and sleep0 modes release page 28 2. operational description 2.2 system clock controller TMP86FS28FG 2.2.4.4 slow mode slow mode is controlled by the sy stem control register 2 (syscr2). the following is the methods to switch the mode with the warm-up counter. (1) switching from normal2 mode to slow1 mode first, set syscr2 page 29 TMP86FS28FG (2) switching from slow1 mode to normal2 mode note: after sysck is cleared to ?0?, executing the in structions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. first, set syscr2 page 30 2. operational description 2.2 system clock controller TMP86FS28FG figure 2-14 switching between the normal2 and slow modes set (syscr2). 7 normal2 mode clr (syscr2). 7 set (syscr2). 5 normal2 mode turn off (a) switching to the slow mode slow1 mode slow2 mode clr (syscr2). 5 (b) switching to the normal2 mode high- frequency clock low- frequency clock main system clock instruction execution sysck xen high- frequency clock low- frequency clock main system clock instruction execution sysck xen slow1 mode warm up during slow2 mode page 31 TMP86FS28FG 2.3 reset circuit the TMP86FS28FG has four types of reset generation procedur es: an external reset input, an address trap reset, a watchdog timer reset and a system clock re set. of these reset, the address trap reset, the watchdog timer and the sys- tem clock reset are a malfunction reset. when the malfunction reset request is detected, reset occurs during the max- imum 24/fc[s]. the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial- ized when power is turned on. therefore, reset may occur during maximum 24/fc[s] (1.5 p s at 16.0 mhz) when power is turned on. table 2-3 shows on-chip hardware initialization by reset action. 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at ?l? level for at least 3 machin e cycles (12/fc [s]) wi th the power supply volt- age within the operating voltage range and oscillation stab le, a reset is applied and the internal state is initial- ized. when the reset pin input goes high, the reset operation is rele ased and the program execution starts at the vector address stored at addresses fffeh to ffffh. figure 2-15 reset circuit table 2-3 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized jump status flag (jf) not initialized watchdog timer enable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flags (ef) 0 control registers refer to each of control register interrupt latches (il) 0 lcd data buffer not initialized ram not initialized internal reset reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset page 32 2. operational description 2.3 reset circuit TMP86FS28FG 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (when wdtcr1 page 33 TMP86FS28FG page 34 2. operational description 2.3 reset circuit TMP86FS28FG page 35 TMP86FS28FG 3. interrupt control circuit the TMP86FS28FG has a total of 23 inte rrupt sources excluding reset. interrup ts can be nested with priorities. four of the internal interrupt sources ar e non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by th e generation of its interrupt request wh ich requests the cpu to accept its inter- rupts. interrupts are enabled or disabled by software using the interrupt master enable fl ag (imf) and in terrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. note 1: to use the address trap interrupt (intatrap), clear wdtcr1 page 36 3. interrupt control circuit 3.1 interrupt latches (il29 to il2) TMP86FS28FG 3.1 interrupt latches (il29 to il2) an interrupt latch is provided for eac h interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. when interrupt request is genera ted, the latch is set to ?1?, and the cpu is requested to accept the interrupt if its interrupt is enabled. the interrupt latch is cleared to "0" immediately after accepting inter- rupt. all interrupt latches are initialized to ?0? during reset. the interrupt latches are located on address 002eh, 002fh, 003ch and 003dh in sfr area. each latch can be cleared to "0" individually by instruction. however, il2 and il3 should not be cleared to "0" by software. for clear- ing the interrupt latch, load instruction should be used and then il2 and il3 should be set to "1". if the read-modify- write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requeste d while such instructions are executed. interrupt latches are not set to ?1? by an instruction. since interrupt latches can be read, the status fo r interrupt requests can be monitored by software. note: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf new ly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0 " automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple inte rrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". 3.2 interrupt enab le register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except fo r the non-maskable interrupts (software interrupt, undefined instruction interr upt, address trap interrupt and watchdog interrupt). non- maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt mast er enable flag (imf) and the individua l interrupt enable flags (ef). these registers are located on address 002ch, 002dh, 003ah and 003bh in sfr area, and they can be read and written by an instructions (including read-modify-write instruc tions such as bit manipulation or operation instructions). 3.2.1 interrupt ma ster enable flag (imf) the interrupt enable register (imf ) enables and disables the acceptance of the whole maskable interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest status on imf is stacked. thus the maskable inter- rupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrup t acceptance, is loaded on imf again. the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cl eared by [ei] and [di] instruction respectively. during reset, the imf is initial- ized to ?0?. example 1 :clears interrupt latches di ; imf m 0 ldw (ill), 111010000011 1111b ; il12, il10 to il6 m 0 ei ; imf m 1 example 2 :reads interrupt latchess ld wa, (ill) ; w m ilh, a m ill example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset page 37 TMP86FS28FG 3.2.2 individual interrupt enable flags (ef29 to ef4) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to ?1? enables acceptan ce of its interrupt, and setting the bit to ?0? dis- ables acceptance. during reset, all the i ndividual interrupt enable flags (ef29 to ef4) ar e initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf become s "0" automatically, clearing imf need not execute nor- mally on interrupt service routine. however, if using mult iple interrupt on interrupt service routine, manipulat- ing ef or il should be executed before setting imf="1". example 1 :enables interrupts individually and sets imf di ; imf m 0 ldw : (eirl), 1110100010100000b ; ef15 to ef13, ef11, ef7, ef5 m 1 note: imf should not be set. : ei ; imf m 1 example 2 :c compiler description example unsigned int _io (3ah) eirl; /* 3ah shows eirl address */ _di(); eirl = 10100000b; : _ei(); page 38 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP86FS28FG note 1: to clear any one of bits il7 to il4, be sure to write "1" into il2 and il3. note 2: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". note 3: do not clear il with read-modify-w rite instructions such as bit operations. note 1: *: don?t care note 2: do not set imf and the interrupt enable flag (ef15 to ef4) to ?1? at the same time. note 3: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". interrupt latches (initial value: 00000000 000000**) ilh,ill (003dh, 003ch) 1514131211109876543210 il15 il14 il13 il12 il11 il10 il9 il8 il7 il6 il5 il4 il3 il2 ilh (003dh) ill (003ch) (initial value: 00000000 00000000) ild,ile (002fh, 002eh) 1514131211109876543210 il31 il30 il29 il28 il27 il26 il25 il24 il23 il22 il21 il20 il19 il18 il17 il16 ild (002fh) ile (002eh) il29 to il2 interrupt latches at rd 0: no interrupt request 1: interrupt request at wr 0: clears the interrupt request 1: (interrupt latch is not set.) r/w interrupt enable registers (initial value: 00000000 0000***0) eirh,eirl (003bh, 003ah) 1514131211109876543210 ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 ef7 ef6 ef5 ef4 imf eirh (003bh) eirl (003ah) (initial value: 00000000 00000000) eird,eire (002dh, 002ch) 1514131211109876543210 ef31 ef30 ef29 ef28 ef27 ef26 ef25 ef24 ef23 ef22 ef21 ef20 ef19 ef18 ef17 ef16 eird (002dh) eire (002ch) ef29 to ef4 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts page 39 TMP86FS28FG 3.3 interrupt sequence an interrupt request, which raised inte rrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruct ion. interrupt acceptance sequence requires 8 machine cycles (2 p s @16 mhz) after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance proc essing is packaged as follows. a. the interrupt master enab le flag (imf) is cleared to ?0? in or der to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. c. the contents of the program coun ter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of psw + imf, pch, pcl. mean- while, the stack pointer (s p) is decremented by 3. d. the entry address (interrupt vect or) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. the instruction stored at the entry address of the inte rrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address entry address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s ] or 38/fs [s] at maximum (if the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return in terrupt instruction example: correspondence be tween vector table address for inttbt an d the entry address of the interrupt service program figure 3-2 vector table address,entry address a b a c + 1 execute instruction sp pc execute instruction n n ? 2 n - 3 n ? 2n ? 1 n ? 1 n a + 2 a + 1 c + 2 b + 3 b + 2 b + 1 a + 1 a a ? 1 execute reti instruction interrupt acceptance execute instruction interrupt service task 1-machine cycle interrupt request interrupt latch (il) imf d2h 03h d203h d204h 06h vector table address entry address 0fh vector interrupt service program fff2h fff3h page 40 3. interrupt control circuit 3.3 interrupt sequence TMP86FS28FG a maskable interrupt is not accepted until the imf is set to ?1? even if th e maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sources are selectively en abled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interr upt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automati cally saved on the stack, but the accumulato r and others are not. these registers are saved by software if necessary. when multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. the fo llowing methods are used to save/restore the general- purpose registers. 3.3.2.1 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested , general-purpose registers can be saved/restored using the push/pop instructions. figure 3-3 save/store register using push and pop instructions 3.3.2.2 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. example :save/store register us ing push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return pcl pch psw at acceptance of an interrupt at execution of push instruction at execution of reti instruction at execution of pop instruction b-4 b-3 b-2 b-1 b pcl pch psw pcl pch psw sp address (example) sp sp sp a w b-5 page 41 TMP86FS28FG figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. as for address trap interrupt (intatrap), it is requir ed to alter stacked data for program counter (pc) to restarting address, during interrupt service program. note:if [retn] is executed with the above data unaltered, the program returns to the address trap area and intatrap occurs again.when interrupt acceptance pr ocessing has completed, stacked data for pcl and pch are located on address (sp + 1) and (sp + 2) respectively. example :save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return [reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. example 1 :returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return interrupt acceptance interrupt service task restoring registers saving registers interrupt return saving/restoring general-purpose registers using push/pop data transfer instruction main task page 42 3. interrupt control circuit 3.4 software interrupt (intsw) TMP86FS28FG interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediat ely after the interrupt retu rn instruction is executed. note 1: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return inter- rupt instruction [retn] is not utilized during inte rrupt service program under intatrap (such as example 2). note 2: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.4 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is th e swi instruction, so a software interrupt is gener- ated and an address error is detect ed. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 3.5 undefined instruct ion interrupt (intundef) taking code which is not defined as authorized instru ction for instruction causes intundef. intundef is gen- erated when the cpu fetches such a co de and tries to execute it. intundef is accepted even if non-maskable inter- rupt is in process. contemporary process is broken and intundef interrupt process starts, soon after it is requested. note: the undefined instruction interrupt (intundef) forces cpu to jump into vector address, as software interrupt (swi) does. 3.6 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructio ns (address trapped area) cause s reset output or address trap interrupt (intatrap). intatrap is accepted even if non-maskable interrupt is in process. contemporary pro- cess is broken and intatrap interrupt pro cess starts, soon afte r it is requested. note: the operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (wdtcr). example 2 :restarting without returning interrupt (in this case, psw (includes imf) befo re interrupt acceptance is discarded.) pintxx: inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to ?1? or clear it to ?0? jp restart address ; jump into restarting address page 43 TMP86FS28FG 3.7 external interrupts the TMP86FS28FG has 6 external interrupt inputs. these inputs are equipped with digital noise reject circuits (pulse inputs of less than a certa in time are elimin ated as noise). edge selection is also possible with int1 to int4. the int0 /p30 pin can be configured as either an external inter- rupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0 /p30 pin function selection are performed by the external interrupt control register (eintcr). note 1: in normal1/2 or idle1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "si g- nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. note 2: when int0en = "0", il4 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an out put and a change occurs in data or input/output status, an inter - rupt request signal is generated in a pseudo manner. in this ca se, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. source pin enable conditions release edge (level) digital noise reject int0 int0 imf ? ef4 ? int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int1 int1 imf ? ef5 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimi- nated as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int2 int2 imf ? ef11 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int3 int3 imf ? ef22 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int4 int4 imf ? ef25 = 1 falling edge, rising edge, falling and rising edge or h level pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int5 int5 imf ? ef26 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. page 44 3. interrupt control circuit 3.7 external interrupts TMP86FS28FG note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the system clock frequency is switched between high and low or when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operat e normally. it is recommended that external interrupts are dis- abled using the interrupt enable register (eir). note 3: the maximum time from modifying int1 nc until a noise reject time is changed is 2 6 /fc. note 4: in case reset pin is released while the state of int4 pin keeps "h" level, the external interrupt 4 request is not generated even if the int4 edge select is specified as "h" level. the rising edge is needed after reset pin is released. external interrupt control register eintcr76543210 (0037h) int1nc int0en int4es int3es int2es int1es (initial value: 0000 000*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p30/ int0 pin configuration 0: p30 input/output port 1: int0 pin (port p30 should be set to an input mode) r/w int4 es int4 edge select 00: rising edge 01: falling edge 10: rising edge and falling edge 11: h level r/w int3 es int3 edge select 0: rising edge 1: falling edge r/w int2 es int2 edge select 0: rising edge 1: falling edge r/w int1 es int1 edge select 0: rising edge 1: falling edge r/w page 45 TMP86FS28FG 4. special function register (sfr) the TMP86FS28FG adopts the memory ma pped i/o system, and all peripheral control and data transfers are per- formed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 0f00h to 0fffh. this chapter shows the arrangement of the special functi on register (sfr) and data buffer register (dbr) for TMP86FS28FG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h p4dr 0005h p5dr 0006h p6dr 0007h p7dr 0008h p8dr 0009h tc3cr 000ah tc4cr 000bh tc5cr 000ch tc6cr 000dh reserved 000eh reserved 000fh reserved 0010h tc10dral 0011h tc10drah 0012h tc10drbl 0013h tc10drbh 0014h tc10cr 0015h ttreg3 0016h ttreg4 0017h ttreg5 0018h ttreg6 0019h pwreg3 001ah pwreg4 001bh pwreg5 001ch pwreg6 001dh reserved 001eh reserved 001fh reserved 0020h tc11dral 0021h tc11drah 0022h tc11drbl 0023h tc11drbh 0024h tc11cr 0025h reserved page 46 4. special function register (sfr) 4.1 sfr TMP86FS28FG note 1: do not access reserved areas by the program. note 2: ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 0026h reserved 0027h reserved 0028h reserved 0029h reserved 002ah reserved 002bh p3outcr 002ch eire 002dh eird 002eh ile 002fh ild 0030h reserved 0031h - stopcr 0032h p0outcr 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh reserved 003fh psw address read write page 47 TMP86FS28FG 4.2 dbr address read write 0f00h reserved : : : : 0f5fh reserved address read write 0f60h siobr0 0f61h siobr1 0f62h siobr2 0f63h siobr3 0f64h siobr4 0f65h siobr5 0f66h siobr6 0f67h siobr7 0f68h - siocr1 0f69h siosr siocr2 address read write 0f70h reserved : : : : 0f7fh reserved page 48 4. special function register (sfr) 4.2 dbr TMP86FS28FG address read write 0f80h reserved : : : : 0f9fh reserved address read write 0fa0h reserved 0fa1h reserved 0fa2h reserved 0fa3h reserved 0fa4h reserved 0fa5h reserved 0fa6h reserved 0fa7h reserved 0fa8h reserved 0fa9h reserved 0faah reserved 0fabh reserved 0fach reserved 0fadh reserved flsstb 0faeh reserved 0fafh flscr 0fb0h reserved 0fb1h reserved 0fb2h reserved 0fb3h reserved 0fb4h reserved 0fb5h reserved 0fb6h reserved 0fb7h reserved 0fb8h reserved 0fb9h reserved 0fbah reserved 0fbbh reserved 0fbch reserved 0fbdh reserved 0fbeh reserved 0fbfh reserved page 49 TMP86FS28FG address read write 0fc0h seg1/0 0fc1h seg3/2 0fc2h seg5/4 0fc3h seg7/6 0fc4h seg9/8 0fc5h seg11/10 0fc6h seg13/12 0fc7h seg15/14 0fc8h seg17/16 0fc9h seg19/18 0fcah seg21/20 0fcbh seg23/22 0fcch seg25/24 0fcdh seg27/26 0fceh seg29/28 0fcfh seg31/30 0fd0h seg33/32 0fd1h seg35/34 0fd2h seg37/36 0fd3h seg39/38 0fd4h p4lcr 0fd5h p5lcr 0fd6h p6lcr 0fd7h p7lcr 0fd8h p8lcr 0fd9h lcdcr 0fdah reserved 0fdbh reserved 0fdch reserved 0fddh reserved 0fdeh reserved 0fdfh reserved page 50 4. special function register (sfr) 4.2 dbr TMP86FS28FG note 1: do not access reserved areas by the program. note 2: ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). address read write 0fe0h adcdr2 - 0fe1h adcdr1 - 0fe2h adccr1 0fe3h adccr2 0fe4h reserved 0fe5h uart0sr uart0cr1 0fe6h - uart0cr2 0fe7h rd0buf td0buf 0fe8h uart1sr uart1cr1 0fe9h - uart1cr2 0feah rd1buf td1buf 0febh reserved 0fech reserved 0fedh reserved 0feeh reserved 0fefh reserved 0ff0h p0prd - 0ff1h reserved 0ff2h p2prd - 0ff3h p3prd - 0ff4h p4prd - 0ff5h p5prd - 0ff6h p6prd - 0ff7h p7prd - 0ff8h p8prd - 0ff9h p1cr1 0ffah p1cr2 0ffbh p4outcr 0ffch p5outcr 0ffdh p6outcr 0ffeh p7outcr 0fffh p8outcr page 51 TMP86FS28FG 5. i/o ports the TMP86FS28FG has 9 input/output ports (62 pins) as shown below. table 5-1 port functions primary function secondary functions port p0 3-bit input/output port external interrupt input, ppg output port p1 8-bit input/output port analog input, stop mode release signal input port p2 3-bit input/output port external interrupt input, low-freque ncy resonator connection, stop mode release signal input port p3 8-bit input/output port external interrupt input, timer/counter input, serial interface input/output, uart input/output, divider output port p4 8-bit input/output port external interrupt input, timer/counter input, lcd segment output, ppg output port p5 8-bit input/output port timer/counter input/output, lcd segment output, uart input/output port p6 8-bit input/output port lcd segment output port p7 8-bit input/output port lcd segment output port p8 8-bit input/output port lcd segment output table 5-2 register list port latch read pch control cr1 cr2 lcd control p0 p0dr (0000h) p0prd (0ff0h) p0outcr (0032h) p1 p1dr (0001h) p1cr1 (0ff9h) p1cr2 (0ffah) p2 p2dr (0002h) p2prd (0ff2h) p3 p3dr (0003h) p3prd (0ff3h) p3outcr (002bh) p4 p4dr (0004h) p4prd (0ff4h) p4outcr (0ffbh) p4lcr (0fd4h) p5 p5dr (0005h) p5prd (0ff5h) p5outcr (0ffch) p5lcr (0fd5h) p6 p6dr (0006h) p6prd (0ff6h) p6outcr (0ffdh) p6lcr (0fd6h) p7 p7dr (0007h) p7prd (0ff7h) p7outcr (0ffeh) p7lcr (0fd7h) p8 p8dr (0008h) p8prd (0ff8h) p8outcr (0fffh) p8lcr (0fd8h) page 52 5. i/o ports TMP86FS28FG each output port contains a latch for holding output data. all input ports do not have latches, making it necessary to externally hold input data until it is read externally or to read input data multiple times before it is processed. fig- ure 5-1 shows input/output timings. external data is read from an input/output port in the s1 state of the read cycle in in struction execution. since this timing cannot be recognized externally, transient input such as chattering must be processed by software. data is out- put to an input/output port in the s2 state of the write cycle in instruction execution. note: the positions of the read and write c ycles may vary depending on the instruction. figure 5-1 input/output timings (example) instruction execution cycle input strobe data input ex: ld a, (x) fetch cycle fetch cycle read cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 instruction execution cycle output latch pulse data output ex: ld (x), a fetch cycle fetch cycle write cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 (a) input timing (b) output timing page 53 TMP86FS28FG 5.1 port p0 (p00 to p02) port p0 is a 3-bit input/output port that can also be used for external interrupt input or ppg output. a reset initializes the output latch (p0dr) to ?1? and the pch control (p0outcr) to ?0?. to use a pin in port p0 as an input po rt or external interrupt input, set p0dr to ?1? and then set the corresponding bit in p0outcr to ?0?. to use a pin in port p0 as a ppg output, set p0dr to ?1?. the output circuit of port p0 can be se t either as sink open-drain output (?0?) or cmos output (?1?) individually for each bit in p0outcr. port p0 has a separate data input register. the output latch state can be read from the p0dr register, and the pin state can be read from the p0prd register. figure 5-2 port p0 table 5-3 register programming for port p0 (p00 to p02) function programmed value p0dr p0outcr port input, external interrupt input ?1? ?0? port "0" output ?0? set as appropriate. port "1" output, ppg output ?1? data input (p0prd) output latch read (p0dr) stop outen p0outcri input data output (p0dr) p0outcri p0i note) i = 2~0 dq dq control output control input output latch page 54 5. i/o ports 5.1 port p0 (p00 to p02) TMP86FS28FG p0dr (0000h) r/w 76543210 p02 ppg1 int3 p01 p00 (initial value: **** *111) p0outcr (0032h) r/w 76543210 (initial value: **** *000) p0outcr port p0 input/output control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p0prd (0ff0h) 76543210 p02 p01 p00 (initial value: **** *000) read only page 55 TMP86FS28FG 5.2 port p1 (p10 to p17) port p1 is an 8-bit input/output port that can be configured as an input or an output on a bit basis. port p1 is also used for analog input or key-on wake-up input. the port p1 input/output control register (p1cr1) and port p1 input control register (p1cr2) are used to specify the function of each pin. a reset initializes p1cr1 to ?0?, p1cr2 to ?1?, and the output latch (p1dr) to ?0? so that port p1 becomes an input port. to use a pin in port p1 as an input por t, set p1cr1 to ?0? and then set p1cr2 to ?1?. to use a pin in port p1 as an analog input or key-on wake-up input, set p1cr1 to ?0? and then set p1cr2 to ?0?. to use a pin in port p1 as an output port, set the corresponding bit in p1cr1 to ?1?. to read the output latch data, set p1cr1 to ?1?and read p1dr. to read the pin state, set p1cr1 to ?0? and p1cr2 to ?1? and then read p1dr. when p1cr1 = ?0 ? and p1cr2 = ?0?, p1dr is read as ?0?. bits not used as analog inputs are used as input/output pins. during ad conversion, however, output instructions must not be executed to ensure the accur acy of conversion results. also, duri ng ad conversion, do not input signals that fluctuate widely to pins near analog input pins. note: an asterisk (*) indicates that either ?1? or ?0? can be set. table 5-4 register programming for port p1 (p10 to p17) function programmed value p1dr p1cr1 p1cr2 port input * ?0? ?1? analog input, key-on wake-up input * ?0? ?0? port ?0? output ?0? ?1? * port "1" output ?1? ?1? * table 5-5 values read from p1dr according to register programming conditions values read from p1dr p1cr1 p1cr2 ?0? ?0? ?0? ?0? ?1? pin state ?1? ?0? output latch state ?1? page 56 5. i/o ports 5.2 port p1 (p10 to p17) TMP86FS28FG figure 5-3 port p1 note 1: pins set to input mode read the pin input data. therefore, when both input and output modes are used in port p1, the contents of the output latch of a pin set to input mode may be overwritten by a bit manipulation instruction. note 2: for a pin used as an analog input, be sure to clear the corresponding bit in p1cr2 to "0" to prevent flow-through current. note 3: for a pin used as an analog input, do not set p1cr1 to "1" (port output) to prevent the pin from becoming shorted with an external signal. note 4: pins not used as analog inputs c an be used as input/output pins. during ad conversion, however, output instruc- tions must not be executed to ensure the accuracy of conv ersion results. also, during ad conversion, do not input signals that fluctuate widely to pins near analog input pins. data output (p1dr) data input (p1dr) stop outen ainds sain p1cr2i input p1cr1i input p cr2i p1cr1i p1i note 1) i = 0, 1, 6, 7 : j = 2~5 : k = 2~5 note 2) stop = bit 7 in syscr1 note 3) sain = ad input select signal note 4) stopk = input select signal for key-on wake-up key-on wake-up data output (p1dr) data input (p1dr) stop stopk outen ainds sain p1cr2j input p1cr1j input p1cr2j p1cr1j p1j dq dq dq dq dq dq analog input analog input page 57 TMP86FS28FG p1dr (0001h) r/w 76543210 p17 ain7 p16 ain6 p15 ain5 stop5 p14 ain4 stop4 p13 ain3 stop3 p12 ain2 stop2 p11 ain1 p10 ain0 (initial value: 0000 0000) p1cr1 (0ff9h) 76543210 (initial value: 0000 0000) p1cr1 port p1 input/output control (set for each bit individually) 0: port input, key-on wake-up input, analog input 1: port output r/w p1cr2 (0ffah) 76543210 (initial value: 1111 1111) p1cr2 port p1 input control (set for each bit individually) 0: analog input, key-on wake-up input 1: port input r/w page 58 5. i/o ports 5.3 port p2 (p20 to p22) TMP86FS28FG 5.3 port p2 (p20 to p22) port p2 is a 3-bit input/output port that can also be used for external interrupt input, stop mode release signal input, or low-frequency resonator connection. to use port p2 as an input port or function pins, set the ou tput latch (p2dr) to ?1?. a reset initializes p2dr to ?1?. in the dual clock mode, pins p21 (xti n) and p22 (xout) are co nnected with a low-frequency resonator (32.768 khz). in the single clock mode, pins p21 and p22 can be used as normal input/output port pins. it is recommended that pin p20 be used as an external interrupt input, stop release signal input, or input port. (when p20 is used as an output port, the interrupt la tch is set on the falling edge of the output pulse.) port p2 has a separate data input register. the output latch state can be read from the p2dr register, and the pin state can be read from the p2prd register. when a read instruction is executed on p2dr or p2prd, bits 7 to 3 are read as undefined. figure 5-4 port p2 note: since pin p20 is also used as a stop pin, the output of p20 becomes high-impedance in stop mode regardless of the outen state. p2dr (0002h) r/w 76543210 p22 xtout p21 xtin p20 int5 stop (initial value: **** *111) p2prd (0ff2h) read only 76543210 p22 p21 p20 data input (p20prd) output latch read (p21) data output (p21) data output (p20) data input (p20) data input (p21prd) output latch read (p22) data input (p22prd) data output (p22) stop outen xten fs p22 (xtout) p21 (xtin) p20 (int5, stop) control input output latch output latch output latch osc. enable dq dq dq page 59 TMP86FS28FG 5.4 port p3 (p30 to p37) port p3 is an 8-bit input/output port that can also be used for external interrupt input, divider output, timer/counter input, serial interface input/o utput, or uart input/output. a reset initializes the output latch (p3dr) to ?1? and the pch control (p3outcr) to ?0?. to use a pin in port p3 as an external interrupt input, timer/counter input, serial inte rface input, or uart input, set p3dr to ?1? and then set the corresponding bit in p3outcr to ?0?. to use a pin in port p3 as a di vider output, seri al interface output, or uart output, set p3dr to ?1?. port 3 can be used for either sio or uart, so be sure not to enable both of these functions at the same time. the output circuit of port p3 can be se t either as sink open-drain output (?0?) or cmos output (?1?) individually for each bit in p3outcr. port p3 has a separate data input register. the output latch state can be read from the p3dr register, and the pin state can be read from the p3prd register. figure 5-5 port p3 table 5-6 register programming for port p3 (p30 to p37) function programmed value p3dr p3outcr port input, external interrupt input, timer/counter input, serial interface input, uart input ?1? ?0? port ?0? output ?0? set as appropriate. port ?1? output, serial interface output, uart output, divider output ?1? data input (p3prd) output latch read (p3dr) stop outen p3outcri input data output (p3dr) p3outcri p3i note) i = 7~0 control output control input output latch dq dq page 60 5. i/o ports 5.4 port p3 (p30 to p37) TMP86FS28FG p3dr (0003h) r/w 76543210 p37 tc10 int4 p36 sck p35 si txd1 p34 so rxd1 p33 p32 p31 dvo p30 int0 (initial value: 1111 1111) p3outcr (002bh) 76543210 (initial value: 0000 0000) p3outcr port p3 output circuit control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p3prd (0ff3h) read only 76543210 p37 p36 p35 p34 p33 p32 p31 p30 page 61 TMP86FS28FG 5.5 port p4 (p40 to p47) port p4 is an 8-bit input/output port that can also be us ed for external interrupt input, ppg output, timer/counter input, or lcd segment output. a reset initializes the output latch (p4dr) to ?1?, the pc h control (p4outcr) to ?0?, and the lcd output control register (p4lcr) to ?0?. to use a pin in port p4 as an input port, external interrupt input, or timer/counter input, set p4dr to ?1? and then set the corresponding bit in p4lcr and p4outcr to ?0?. to use a pin in port p4 as an lcd segment ou tput, set the corresponding bit in p4lcr to ?1?. to use a pin in port p4 as a ppg out put, set p4dr to ?1? and then set th e corresponding bit in p4lcr to ?0?. the output circuit of port p4 can be se t either as sink open-drain outut (?0?) or cmos output (?1?) individually for each bit in p4outcr. port p4 has a separate data input register. the output latch state can be read from the p4dr register, and the pin state can be read from the p4prd register. note: an asterisk (*) indicates that either ?1? or ?0? can be set. figure 5-6 port p4 table 5-7 register programming for port p4 (p40 to p47) function programmed value p4dr p4outcr p4lcr port input, external interrupt input, timer/counter input ?1? ?0? ?0? port "0" output ?0? set as appropriate. ?0? port ?1? output ?1? ?0? ppg output ?1? ?0? lcd segment output * * ?1? data input (p4prd) output latch read (p4dr) stop outen p4outcri input data output (p4dr) p4outcri p4i note) i = 7~0 dq dq lcd data output p4lcri dq p4lcri input control output control input output latch page 62 5. i/o ports 5.5 port p4 (p40 to p47) TMP86FS28FG p4dr (0004h) r/w 76543210 p47 seg32 p46 seg31 p45 seg30 p44 seg29 p43 seg28 tc11 p42 seg27 ppg1 p41 seg26 int2 p40 seg25 int1 (initial value: 0000 0000) p4lcr (0fd4h) 76543210 (initial value: 0000 0000) p4lcr port p4 segment output control (set for each bit individually) 0: input/output port 1: lcd segment output r/w p4outcr (0ffbh) 76543210 (initial value: 0000 0000) p4outcr p4 output circuit control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p4prd (0ff4h) read only 76543210 p47 p46 p45 p44 p43 p42 p41 p40 page 63 TMP86FS28FG 5.6 port p5 (p50 to p57) port p5 is an 8-bit input/output port that can also be used for timer/counter input/output, lcd segment output, or uart input/output. a reset initializes the output latch (p5dr) to ?1?, the pc h control (p5outcr) to ?0?, and the lcd output control register (p5lcr) to ?0?. to use a pin in port p5 as an input port, timer/counter i nput, or uart input, set p5dr to ?1? and then set the cor- responding bit in p5lcr and p5outcr to ?0?. to use a pin in port p5 as an lcd segment ou tput, set the corresponding bit in p5lcr to ?1?. to use a pin in port p5 as a uart output or timer/counter output, set p5dr to "1" and then set the corresponding bit in p5lcr to ?0?. the output circuit of port p5 can be se t either as sink open-drain output (?0?) or cmos otuput (?1?) individually for each bit in p5outcr. port p5 has a separate data input register. the output latch state can be read from the p5dr register, and the pin state can be read from the p5prd register. note: an asterisk (*) indicates that either ?1? or ?0? can be set. figure 5-7 port p5 table 5-8 register programming for port p5 (p50 to p57) function programmed value p5dr p5outcr p5lcr port input, uart input, timer/counter input ?1? ?0? ?0? port ?0? output ?0? set as appropriate. ?0? port ?1? output, uart output ?1? ?0? lcd segment output * * ?1? data input (p5prd) output latch read (p5dr) stop outen p5outcri input data output (p5dr) p5outcri p5i note) i = 7~0 dq dq lcd data output p5lcri dq p5lcri input control output control input output latch page 64 5. i/o ports 5.6 port p5 (p50 to p57) TMP86FS28FG p5dr (0005h) r/w 76543210 p57 seg24 p56 seg25 p55 seg26 tc6 pwm6 pdo6 p54 seg27 tc5 pwm5 pdo5 p53 seg28 tc4 pwm4 pdo4 p52 seg29 tc3 pwm3 pdo3 p51 seg30 rxd0 p50 seg31 txd0 (initial value: 0000 0000) p5lcr (0fd5h) 76543210 (initial value: 0000 0000) p5lcr port p5 segment output control (set for each bit individually) 0: input/output port 1: lcd segment output r/w p5outcr (0ffch) 76543210 (initial value: 0000 0000) p5outcr port p5 input/output control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p5prd (0ff5h) 76543210 p57 p56 p55 p54 p53 p52 p51 p50 read only page 65 TMP86FS28FG 5.7 port p6 (p60 to p67) port p6 is an 8-bit input/output port that can also be used for lcd segment output. a reset initializes the output latch (p6dr) to ?1?, the pc h control (p6outcr) to ?0?, and the lcd output control register (p6lcr) to ?0?. to use a pin in port p6 as an input port, set p6dr to ?1? and then set the corr esponding bit in p6lcr and p6outcr to ?0?. to use a pin in port p6 as an lcd segment ou tput, set the corresponding bit in p6lcr to ?1?. the output circuit of port p6 can be se t either as sink open-drain output (?0?) or cmos output (?1?) individually for each bit in p6outcr. port p6 has a separate data input register. the outut latc h state can be read from the p6dr register, and the pin state can be read from the p6prd register. note: an asterisk (*) indicates that either ?1? or ?0? can be set. figure 5-8 port p6 table 5-9 register programming for port p6 (p60 to p67) function programmed value p6dr p6outcr p6lcr port input ?1? ?0? ?0? port "0" output ?0? set as appropriate. ?0? port ?1? output ?1? ?0? lcd segment output * * ?1? data input (p6prd) output latch read (p6dr) stop outen p6outcri input data output (p6dr) p6outcri p6i note) i = 7~0 dq dq lcd data output p6lcri dq p6lcri input output latch page 66 5. i/o ports 5.7 port p6 (p60 to p67) TMP86FS28FG p6dr (0006h) r/w 76543210 p67 seg16 p66 seg17 p65 seg18 p64 seg19 p63 seg20 p62 seg21 p61 seg22 p60 seg23 (initial value: 0000 0000) p6lcr (0fd6h) 76543210 (initial value: 0000 0000) p6lcr port p6 segment output control (set for each bit individually) 0: input/output port 1: segment output r/w p6outcr (0ffdh) 76543210 (initial value: 1111 1111) p6cr2 port p6 input/output control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p6prd (0ff6h) 76543210 p67 p66 p65 p64 p63 p62 p61 p60 read only page 67 TMP86FS28FG 5.8 port p7 (p70 to p77) port p7 is an 8-bit input/output port that can also be used for lcd segment output. a reset initializes the output latch (p7dr) to ?1?, the pc h control (p7outcr) to ?0?, and the lcd output control register (p7lcr) to ?0?. to use a pin in port p7 as an input port, set p7dr to ?1? and then set the corr esponding bit in p7lcr and p7outcr to ?0?. to use a pin in port p7 as an lcd segment ou tput, set the corresponding bit in p7lcr to ?1?. the output circuit of port p7 can be se t either as sink open-drain output (?0?) or cmos output (?1?) individually for each bit in p7outcr. port p7 has a separate data input register. the output latch state can be read from the p7dr register, and the pin state can be read from the p7prd register. note: an asterisk (*) indicates that either ?1? or ?0? can be set. figure 5-9 port p7 table 5-10 register programming for port p7 (p70 to p77) function programmed value p7dr p7outcr p7lcr port input ?1? ?0? ?0? port ?0? output ?0? set as appropriate. ?0? port ?1? output ?1? ?0? lcd segment output * * ?1? data input (p7prd) output latch read (p7dr) stop outen p7outcri input data output (p7dr) p7outcri p7i note) i = 7~0 dq dq lcd data output p7lcri dq p7lcri input output latch page 68 5. i/o ports 5.8 port p7 (p70 to p77) TMP86FS28FG p7dr (0007h) r/w 76543210 p77 seg8 p76 seg9 p75 seg10 p74 seg11 p73 seg12 p72 seg13 p71 seg14 p70 seg15 (initial value: 0000 0000) p7lcr (0fd7h) 76543210 (initial value: 0000 0000) p7lcr port p7 segment output control (set for each bit individually) 0: input/output port 1: segment output r/w p7outcr (0ffeh) 76543210 (initial value: 0000 0000) p7outcr port p7 input/output control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p7prd (0ff7h) 76543210 p77 p76 p75 p74 p73 p72 p71 p70 read only page 69 TMP86FS28FG 5.9 port p8 (p80 to p87) port p8 is an 8-bit input/output port that can also be used for lcd segment output. a reset initializes the output latch (p8dr) to ?1?, the pc h control (p8outcr) to ?0?, and the lcd output control register (p8lcr) to ?0?. to use a pin in port p8 as an input port, set p8dr to ?1? and then set the corr esponding bit in p8lcr and p8outcr to ?0?. to use a pin in port p8 as an lcd segment ou tput, set the corresponding bit in p8lcr to ?1?. the output circuit of port p8 can be se t either as sink open-drain output (?0?) or cmos output (?1?) individually for each bit in p8outcr. port p8 has a separate data input register. the output latch state can be read from the p8dr register, and the pin state can be read from the p8prd register. note: an asterisk (*) indicates that either ?1? or ?0? can be set. figure 5-10 port p8 table 5-11 register programming for port p8 (p80 to p87) function port input p8dr p8outcr p8lcr port input ?1? ?0? ?0? port ?0? output ?0? set as appropriate. ?0? port ?1? output ?1? ?0? lcd segment output * * ?1? data input (p8prd) output latch read (p8dr) stop outen p8outcri input data output (p8dr) p8outcri p8i note) i = 7~0 dq dq lcd data output p8lcri dq p8lcri input output latch page 70 5. i/o ports 5.9 port p8 (p80 to p87) TMP86FS28FG p8dr (0008h) r/w 76543210 p87 seg0 p86 seg1 p85 seg2 p84 seg3 p83 seg4 p82 seg5 p81 seg6 p80 seg7 (initial value: 0000 0000) p8lcr (0fd8h) 76543210 (initial value: 0000 0000) p8lcr port p8 segment output control (set for each bit individually) 0: input/output port 1: lcd segment output r/w p8outcr (0fffh) 76543210 (initial value: 0000 0000) p8outcr port p8 input/output control (set for each bit individually) 0: sink open-drain output 1: cmos output r/w p8prd (0ff8h) 76543210 p87 p86 p85 p84 p83 p82 p81 p80 read only page 71 TMP86FS28FG 6. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidl y the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as ?reset request? or ?inter- rupt request?. upon the reset release, this signal is initialized to ?reset request?. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. note: care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 watchdog timer configuration figure 6-1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 19 or fs/2 11 fc/2 17 or fs/2 9 page 72 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86FS28FG 6.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 6.2.1 malfunction detection me thods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as en dless loops or the deadlock condition s occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 page 73 TMP86FS28FG note 1: after clearing wdtout to ?0?, the program cannot set it to ?1?. note 2: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a don?t care is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdten, set the register in accordance wi th the procedures shown in ?6.2.3 watchdog timer disable?. note 1: the disable code is valid only when wdtcr1 page 74 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86FS28FG 6.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the fo llowing procedures . setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to ?0?. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 page 75 TMP86FS28FG 6.2.5 watchdog timer reset when a binary-counter overflow occurs while wdt cr1 page 76 6. watchdog timer (wdt) 6.3 address trap TMP86FS28FG 6.3 address trap the watchdog timer control register 1 and 2 share the a ddresses with the control regi sters to generate address traps. 6.3.1 selection of address tr ap in internal ram (atas) wdtcr1 page 77 TMP86FS28FG 6.3.4 address trap reset while wdtcr1 page 78 6. watchdog timer (wdt) 6.3 address trap TMP86FS28FG page 79 TMP86FS28FG 7. time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). 7.1 time base timer 7.1.1 configuration figure 7-1 time base timer configuration 7.1.2 control time base timer is controlled by time base timer control register (tbtcr). note 1: fc; high-frequency clock [hz], fs ; low-frequency clock [hz], *; don't care time base timer control register 7 6543210 tbtcr (0036h) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 fs/2 15 001 fc/2 21 fs/2 13 fs/2 13 010 fc/2 16 fs/2 8 ? 011 fc/2 14 fs/2 6 ? 100 fc/2 13 fs/2 5 ? 101 fc/2 12 fs/2 4 ? 110 fc/2 11 fs/2 3 ? 111 fc/2 9 fs/2 ? fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 16 or fs/2 8 fc/2 14 or fs/2 6 fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 9 or fs/2 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request idle0, sleep0 release request page 80 7. time base timer (tbt) 7.1 time base timer TMP86FS28FG note 2: the interrupt frequency (tbtck) must be selected with t he time base timer disabled (tbten="0"). (the interrupt fre- quency must not be changed with the disable from the enable state.) both frequency selection and enabling can be per- formed simultaneously. 7.1.3 function an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider output of the timing generator which is selected by tb tck. ) after time base timer has been enabled. the divider is not cleared by the progra m; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 7-2 ). figure 7-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck m 010 ld (tbtcr) , 00001010b ; tbten m 1 di ; imf m 0 set (eirl) . 6 table 7-1 time base timer interrupt frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) tbtck time base timer interrupt frequency [hz] normal1/2, idle1/2 mode normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 000 1.91 1 1 001 7.63 4 4 010 244.14 128 ? 011 976.56 512 ? 100 1953.13 1024 ? 101 3906.25 2048 ? 110 7812.5 4096 ? 111 31250 16384 ? source clock enable tbt interrupt period tbtcr page 81 TMP86FS28FG 7.2 divider output ( dvo ) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. 7.2.1 configuration figure 7-3 divider output 7.2.2 control the divider output is controlled by the time base timer control register. note: selection of divider output frequency (dvock) must be made whil e divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequen cy from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. time base timer control register 7654 321 0 tbtcr (0036h) dvoen dvock (dv7ck) (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo ) frequency selection: [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 13 fs/2 5 fs/2 5 01 fc/2 12 fs/2 4 fs/2 4 10 fc/2 11 fs/2 3 fs/2 3 11 fc/2 10 fs/2 2 fs/2 2 tbtcr output latch port output latch mpx dvoen tbtcr page 82 7. time base timer (tbt) 7.2 divider output (dvo) TMP86FS28FG example :1.95 khz pulse output (fc = 16.0 mhz) ld (tbtcr) , 00000000b ; dvock m "00" ld (tbtcr) , 10000000b ; dvoen m "1" table 7-2 divider output frequency ( exam ple : fc = 16.0 mhz, fs = 32.768 khz ) dvock divider output frequency [hz] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 00 1.953 k 1.024 k 1.024 k 01 3.906 k 2.048 k 2.048 k 10 7.813 k 4.096 k 4.096 k 11 15.625 k 8.192 k 8.192 k page 83 TMP86FS28FG 8. 16-bit timercounter (tc10,tc11) 8.1 16-bit timercounter 10 8.1.1 configuration figure 8-1 timercounter 10 (tc10) :::?:w :w pin tc1 :?:w:?::? mett10 start capture clear source :w :w clock ppg output mode write to tc10cr 16-bit up-counter clear tc10drb selector tc10dra tc10cr tc10 control register match inttc10 interript tff10 acap10 tc10ck window mode set t oggl e q 2 t oggl e set clear q y a d b c s b a y s tc10s clear mppg10 ppg output mode internal reset s enable mcap10 s y a b tc10s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11, fs/2 3 fc/2 7 fc/2 3 page 84 8. 16-bit timercounter (tc10,tc11) 8.1 16-bit timercounter 10 TMP86FS28FG 8.1.2 timercounter control the timercounter 10 is controlled by the timercounter 10 control register (tc10cr) and two 16-bit timer registers (tc10dra and tc10drb). note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: the timer register consists of two shift registers. a va lue set in the timer register becomes valid at the rising edge o f the first source clock pulse that occurs after the upper byte (tc10drah and tc10drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). writing only the lower byte (tc10dral and tc10drbl) does not enable the setting of the timer register. note 3: to set the mode, source clock, ppg output control and timer f/f control, write to tc10cr1 during tc10s=00. set the timer f/f10 control until the first ti mer start after setting the ppg mode. timer register 1514131211109876543210 tc10dra (0011h, 0010h) tc10drah (0011h) tc10dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc10drb (0013h, 0012h) tc10drbh (0013h) tc10drbl (0012h) (initial value: 1111 1111 1111 1111) read/write (write e nabled only in the ppg output mode) timercounter 10 control register tc10cr (0014h) 7 6 543210 tff10 acap10 mcap10 mett10 mppg10 tc10s tc10ck tc10m read/write (initial value: 0000 0000) tff10 timer f/f10 control 0: clear 1: set r/w acap10 auto capture control 0:auto-capture disable 1:auto-capture enable r/w mcap10 pulse width measure- ment mode control 0:double edge capture 1:single edge capture mett10 external trigger timer mode control 0:trigger start 1:trigger start and stop mppg10 ppg output control 0:continuous pulse generation 1:one-shot tc10s tc10 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear oooooo 01: command start o????o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) ? ooooo 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) ? ooooo tc10ck tc10 source clock select [hz] normal1/2, idle1/2 mode divider slow, sleep mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 11 fs/2 3 dv9 fs/2 3 01 fc/2 7 fc/2 7 dv5 ? 10 fc/2 3 fc/2 3 dv1 ? 11 external clock (tc10 pin input) tc10m tc10 operating mode select 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w page 85 TMP86FS28FG note 4: auto-capture can be used only in t he timer, event counter, and window modes. note 5: to set the timer registers, the following relationship must be satisfied. tc10dra > tc10drb > 1 (ppg output mode), tc10dra > 1 (other modes) note 6: set tff10 to ?0? in the mode except ppg output mode. note 7: set tc10drb after setting tc10m to the ppg output mode. note 8: when the stop mode is entered, the start control (tc10s) is cleared to ?00? automatically , and the timer stops. after th e stop mode is exited, set the tc10s to use the timer counter again. note 9: use the auto-capture function in the operative condition of tc10. a captured value may not be fixed if it's read after t he execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 10:since the up-counter value is captured into tc10drb by the source clock of up-counter after setting tc10cr page 86 8. 16-bit timercounter (tc10,tc11) 8.1 16-bit timercounter 10 TMP86FS28FG note: since the up-counter value is captured into tc10drb by t he source clock of up-counter after setting tc10cr page 87 TMP86FS28FG 8.1.3.2 external trigger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc10 pin, and counts up at the edge of the internal cl ock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc10cr page 88 8. 16-bit timercounter (tc10,tc11) 8.1 16-bit timercounter 10 TMP86FS28FG figure 8-3 external tri gger timer mode timing chart inttc10 interrupt request source clock up-counter tc10dra tc10 pin input inttc10 interrupt request source clock up-counter tc10dra tc10 pin input 0 at the rising edge (tc10s = 10) at the rising edge (tc10s = 10) (a) trigger start (mett10 = 0) count start match detect count start 0 1234 23 n (b) trigger start and stop (mett10 = 1) count start count start 0 123 m 0 n n 0 count clear note: m < n count clear 123 1 n m - 1 n - 1 match detect count clear page 89 TMP86FS28FG 8.1.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc10 pin. either the rising or falling edge of the input pulse is selected as the count up edge in tc10cr page 90 8. 16-bit timercounter (tc10,tc11) 8.1 16-bit timercounter 10 TMP86FS28FG 8.1.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc10 pin (window pulse) and the internal source clock. either the posi- tive logic (count up during high-going pulse) or ne gative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc10dra value is detected, an inttc10 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock pro- grammed with tc10cr page 91 TMP86FS28FG 8.1.3.5 pulse width measurement mode in the pulse width measurement mode, the up-counter st arts counting by the input pulse triggering of the tc10 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc10cr page 92 8. 16-bit timercounter (tc10,tc11) 8.1 16-bit timercounter 10 TMP86FS28FG example :duty measurem ent (resolution fc/2 7 [hz]) clr (inttc10sw). 0 ; inttc10 service switch initial setting address set to convert inttc10sw at each inttc10 ld (tc10cr), 00000110b ; sets the tc10 mode and source clock di ; imf ?0? set (eirl). 7 ; enables inttc10 ei ; imf ?1? ld (tc10cr), 00100110b ; starts tc10 with an external trigger at mcap10 = 0 : pinttc10: cpl (inttc10sw). 0 ; inttc10 interrupt, inverts and tests inttc10 service switch jrs f, sinttc10 ld a, (tc10drbl) ; reads tc10drb (high-level pulse width) ld w,(tc10drbh) ld (hpulse), wa ; stores high-level pulse width in ram reti sinttc10: ld a, (tc10drbl) ; reads tc10drb (cycle) ld w,(tc10drbh) ld (width), wa ; stores cycle in ram : reti ; duty calculation : vinttc10: dw pinttc10 ; inttc10 interrupt vector width hpulse tc10 pin inttc10 interrupt request inttc10sw page 93 TMP86FS28FG figure 8-6 pulse wi dth measurement mode tc10drb inttc10 interrupt request interrupt request tc10 pin input counter internal clock (mcap10 = "1") 23 n count start count start trigger (tc10s = "10") 1 3 2 1 4 0 n 0 capture n - 1 tc10drb inttc10 tc10 pin input counter internal clock (mcap10 = "0") 12 n count start count start (tc10s = "10") 3 2 1 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture page 94 8. 16-bit timercounter (tc10,tc11) 8.1 16-bit timercounter 10 TMP86FS28FG 8.1.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. to start the timer, tc10cr page 95 TMP86FS28FG figure 8-7 ppg output example :generating a pulse which is high-going for 800 s and low-going for 200 p s (fc = 16 mhz) setting port ld (tc10cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc10dra), 007dh ; sets the cycle (1 ms y 2 7 /fc ms = 007dh) ldw (tc10drb), 0019h ; sets the low-level pulse width (200 p s y 2 7 /fc = 0019h) ld (tc10cr), 10010111b ; starts the timer example :after stopping ppg, setting the ppg pin to a high-level to restart ppg (fc = 16 mhz) setting port ld (tc10cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc10dra), 007dh ; sets the cycle (1 ms y 2 7 /fc p s = 007dh) ldw (tc10drb), 0019h ; sets the low-level pulse width (200 p s y 2 7 /fc = 0019h) ld (tc10cr), 10010111b ; starts the timer :: ld (tc10cr), 10000111b ; stops the timer ld (tc10cr), 10000100b ; sets the timer mode ld (tc10cr), 00000111b ; sets the ppg mode, tff10 = 0 ld (tc10cr), 00010111b ; starts the timer q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc10cr page 96 8. 16-bit timercounter (tc10,tc11) 8.1 16-bit timercounter 10 TMP86FS28FG figure 8-8 pp g mode timing chart inttc10 tc10dra internal clock counter tc10drb tc10dra ppg pin output 0 inttc10 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc10s = 01) tc10drb trigger count start timer start counter internal clock tc10 pin input ppg pin output 01 m n n n + 1 m 0 (b) one-shot pulse generation (tc10s = 10) match detect note: m > n note: m > n [application] one-shot pulse output page 97 TMP86FS28FG 8.2 16-bit timercounter 11 8.2.1 configuration figure 8-9 timercounter 11 (tc11) :::?:w :w pin tc1 :?:w:?::? mett11 start capture clear source :w :w clock ppg output mode write to tc11cr 16-bit up-counter clear tc11drb selector tc11dra tc11cr tc11 control register match inttc11 interript tff11 acap11 tc11ck window mode set t oggl e q 2 t oggl e set clear q y a d b c s b a y s tc11s clear mppg11 ppg output mode internal reset s enable mcap11 s y a b tc11s 2 set clear command start decoder external trigger start edge detector note: function i/o ma y not operate dependin g on i/o port settin g . for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11, fs/2 3 fc/2 7 fc/2 3 page 98 8. 16-bit timercounter (tc10,tc11) 8.2 16-bit timercounter 11 TMP86FS28FG 8.2.2 timercounter control the timercounter 11 is controlled by the timercounte r 11 control register (tc11cr) and two 16-bit timer registers (tc11dra and tc11drb). note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: the timer register consists of two shift registers. a va lue set in the timer register becomes valid at the rising edge o f the first source clock pulse that occurs after the upper byte (t c11drah and tc11drbh) is written. therefore, write the lower timer register 1514131211109876543210 tc11dra (0021h, 0020h) tc11drah (0021h) tc11dral (0020h) (initial value: 1111 1111 1111 1111) read/write tc11drb (0023h, 0022h) tc11drbh (0023h) tc11drbl (0022h) (initial value: 1111 1111 1111 1111) read/write (write e nabled only in the ppg output mode) timercounter 11 control register tc11cr (0024h) 7 6 543210 tff11 acap11 mcap11 mett11 mppg11 tc11s tc11ck tc11m read/write (initial value: 0000 0000) tff11 timer f/f11 control 0: clear 1: set r/w acap11 auto capture control 0:auto-capture disable 1:auto-capture enable r/w mcap11 pulse width measure- ment mode control 0:double edge capture 1:single edge capture mett11 external trigger timer mode control 0:trigger start 1:trigger start and stop mppg11 ppg output control 0:continuous pulse generation 1:one-shot tc11s tc11 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear oooooo 01: command start o????o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) ? ooooo 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) ? ooooo tc11ck tc11 source clock select [hz] normal1/2, idle1/2 mode divider slow, sleep mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 11 fs/2 3 dv9 fs/2 3 01 fc/2 7 fc/2 7 dv5 ? 10 fc/2 3 fc/2 3 dv1 ? 11 external clock (tc11 pin input) tc11m tc11 operating mode select 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w page 99 TMP86FS28FG byte and the upper byte in this order (it is recommended to write the register with a 16-bit acce ss instruction). writing only the lower byte (tc11dral and tc11drbl) does not enable the setting of the timer register. note 3: to set the mode, source clock, ppg output control and timer f/f control, write to tc11cr1 during tc11s=00. set the timer f/f10 control until the first ti mer start after setting the ppg mode. note 4: auto-capture can be used only in t he timer, event counter, and window modes. note 5: to set the timer registers, the following relationship must be satisfied. tc11dra > tc11drb > 1 (ppg output mode), tc11dra > 1 (other modes) note 6: set tff11 to ?0? in the mode except ppg output mode. note 7: set tc11drb after setting tc11m to the ppg output mode. note 8: when the stop mode is entered, the start control (tc11s) is cleared to ?00? automatically, and the timer stops. after th e stop mode is exited, set the tc 11s to use the timer counter again. note 9: use the auto-capture function in the operative condition of tc11. a captured value may not be fixed if it's read after t he execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 10:since the up-counter value is captured into tc11drb by the source clock of up-counter after setting tc11cr page 100 8. 16-bit timercounter (tc10,tc11) 8.2 16-bit timercounter 11 TMP86FS28FG note: since the up-counter value is captured into tc11drb by the source clock of up-counter after setting tc11cr page 101 TMP86FS28FG 8.2.3.2 external trigger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc11 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc11cr page 102 8. 16-bit timercounter (tc10,tc11) 8.2 16-bit timercounter 11 TMP86FS28FG figure 8-11 external tr igger timer mode timing chart inttc11 interrupt request source clock up-counter tc11dra tc11 pin input inttc11 interrupt request source clock up-counter tc11dra tc11 pin input 0 at the rising edge (tc11s = 10) at the rising edge (tc11s = 10) (a) trigger start (mett11 = 0) count start match detect count start 01234 23 n (b) trigger start and stop (mett11 = 1) count start count start 0 123 m 0 n n 0 count clear note: m < n count clear 123 1 n m - 1 n - 1 match detect count clear page 103 TMP86FS28FG 8.2.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc11 pin. either the rising or falling edge of the input pulse is selected as the count up edge in tc11cr page 104 8. 16-bit timercounter (tc10,tc11) 8.2 16-bit timercounter 11 TMP86FS28FG 8.2.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc11 pin (window pulse) and the internal source clock. either the posi- tive logic (count up during high-going pulse) or ne gative logic (count up during low-going pulse) can be selected. when a match between the up-count er and the tc11dra value is de tected, an inttc11 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock pro- grammed with tc11cr page 105 TMP86FS28FG 8.2.3.5 pulse width measurement mode in the pulse width measurement mode, the up-counter st arts counting by the input pulse triggering of the tc11 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc11cr< tc11s>. either the single- or double-edge capture is selected as the trigger edge in tc11cr page 106 8. 16-bit timercounter (tc10,tc11) 8.2 16-bit timercounter 11 TMP86FS28FG example :duty measurem ent (resolution fc/2 7 [hz]) clr (inttc11sw). 0 ; inttc11 service switch initial setting address set to convert inttc11sw at each inttc11 ld (tc11cr), 00000110b ; sets the tc11 mode and source clock di ; imf ?0? set (eirh). 7 ; enables inttc11 ei ; imf ?1? ld (tc11cr), 00100110b ; starts tc11 with an external trigger at mcap11 = 0 : pinttc11: cpl (inttc11sw). 0 ; inttc11 interrupt, inverts and tests inttc11 service switch jrs f, sinttc11 ld a, (tc11drbl) ; reads tc11drb (high-level pulse width) ld w,(tc11drbh) ld (hpulse), wa ; stores high-level pulse width in ram reti sinttc11: ld a, (tc11drbl) ; reads tc11drb (cycle) ld w,(tc11drbh) ld (width), wa ; stores cycle in ram : reti ; duty calculation : vinttc11: dw pinttc11 ; inttc11 interrupt vector width hpulse tc11 pin inttc11 interrupt request inttc11sw page 107 TMP86FS28FG figure 8-14 pulse width measurement mode tc11drb inttc11 interrupt request interrupt request tc11 pin input counter internal clock (mcap11 = "1") 23 n count start count start trigger (tc11s = "10") 1 3 2 1 4 0 n 0 capture n - 1 tc11drb inttc11 tc11 pin input counter internal clock (mcap11 = "0") 12 n count start count start (tc11s = "10") 3 2 1 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture page 108 8. 16-bit timercounter (tc10,tc11) 8.2 16-bit timercounter 11 TMP86FS28FG 8.2.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. to start the timer, tc11cr page 109 TMP86FS28FG figure 8-15 ppg output example :generating a pulse which is high-going for 800 s and low-going for 200 p s (fc = 16 mhz) setting port ld (tc11cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc11dra), 007dh ; sets the cycle (1 ms y 2 7 /fc ms = 007dh) ldw (tc11drb), 0019h ; sets the low-level pulse width (200 p s y 2 7 /fc = 0019h) ld (tc11cr), 10010111b ; starts the timer example :after stopping ppg, setting the ppg pin to a high-level to restart ppg (fc = 16 mhz) setting port ld (tc11cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc11dra), 007dh ; sets the cycle (1 ms y 2 7 /fc p s = 007dh) ldw (tc11drb), 0019h ; sets the low-level pulse width (200 p s y 2 7 /fc = 0019h) ld (tc11cr), 10010111b ; starts the timer :: ld (tc11cr), 10000111b ; stops the timer ld (tc11cr), 10000100b ; sets the timer mode ld (tc11cr), 00000111b ; sets the ppg mode, tff11 = 0 ld (tc11cr), 00010111b ; starts the timer q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc11cr page 110 8. 16-bit timercounter (tc10,tc11) 8.2 16-bit timercounter 11 TMP86FS28FG figure 8-16 ppg mo de timing chart inttc11 tc11dra internal clock counter tc11drb tc11dra ppg pin output 0 inttc11 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc11s = 01) tc11drb trigger count start timer start counter internal clock tc11 pin input ppg pin output 01 m n nn + 1 m 0 (b) one-shot pulse generation (tc11s = 10) match detect note: m > n note: m > n [application] one-shot pulse output page 111 TMP86FS28FG 9. 8-bit timercounter (tc3, tc4) 9.1 configuration figure 9-1 8-bit timercounter 3, 4 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc4cr tc3cr ttreg4 pwreg4 ttreg3 pwreg3 tc3 pin tc4 pin tc4s tc3s inttc3 interrupt request inttc4 interrupt request tff4 tff3 pdo 4/pwm 4/ ppg 4 pin pdo 3/pwm 3/ pin tc3ck tc4ck tc3m tc3s tff3 tc4m tc4s tff4 timer f/f4 timer f/f3 page 112 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86FS28FG 9.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (ttreg3, pwreg3). note 1: do not change the timer register (t treg3) setting while the timer is running. note 2: do not change the timer register (pwreg3) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc3m, tc3ck and tff3 settings while the timer is running. note 3: to stop the timer operation (tc3s= 1 o 0), do not change the tc3m, tc3ck and tff3 settings. to start the timer opera- tion (tc3s= 0 o 1), tc3m, tc3ck and tff3 can be programmed. note 4: to use the timercounter in the 16-bit mode, set th e operating mode by programming tc4cr page 113 TMP86FS28FG note 7: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 9- 3. note 8: the operating clock fc in t he slow or sleep mode can be used only as the high-frequency warm-up mode. page 114 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86FS28FG the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and two 8-bit timer registers (ttreg4 and pwreg4). note 1: do not change the timer register (t treg4) setting while the timer is running. note 2: do not change the timer register (pwreg4) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc4m, tc4ck and tff4 settings while the timer is running. note 3: to stop the timer operation (tc4s= 1 o 0), do not change the tc4m, tc4ck and tff4 settings. to start the timer operation (tc4s= 0 o 1), tc4m, tc4ck and tff4 can be programmed. note 4: when tc4m= 1** (upper byte in the 16-bit mode), the sour ce clock becomes the tc3 over flow signal regardless of the tc4ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc4m, where tc3cr page 115 TMP86FS28FG note 6: to the timercounter in the 16-bit mode, select the so urce clock by programming tc3cr page 116 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86FS28FG note: n = 3 to 4 table 9-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 d (ttregn) d 255 8-bit pdo 1 d (ttregn) d 255 8-bit pwm 2 d (pwregn) d 254 16-bit timer/event counter 1 d (ttreg4, 3) d 65535 warm-up counter 256 d (ttreg4, 3) d 65535 16-bit pwm 2 d (pwreg4, 3) d 65534 16-bit ppg 1 d (pwreg4, 3) < (ttreg4, 3) d 65535 and (pwreg4, 3) + 1 < (ttreg4, 3) page 117 TMP86FS28FG 9.3 function the timercounter 3 and 4 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 3 and 4 (tc3, 4) are cascadable to form a 16- bit timer. the 16-bit timer has the operat ing modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 9.3.1 8-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr page 118 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86FS28FG figure 9-2 8-bit timer mode timing chart (tc4) 9.3.2 8-bit event counter mode (tc3, 4) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj valu e is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr page 119 TMP86FS28FG note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediatel y after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr page 120 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86FS28FG figure 9-4 8-bit pdo mode timing chart (tc4) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc4cr page 121 TMP86FS28FG 9.3.4 8-bit pulse wi dth modulation (pwm) output mode (tc3, 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr page 122 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86FS28FG figure 9-5 8-bit pwm mo de timing chart (tc4) 1 0 nn+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc4cr page 123 TMP86FS28FG 9.3.5 16-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. the timercounter 3 and 4 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg3, ttreg4) valu e is detected after the timer is started by setting tc4cr page 124 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86FS28FG 9.3.6 16-bit event c ounter mode (tc3 and 4) 9.3.7 16-bit pulse width modulatio n (pwm) output mode (tc3 and 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 3 and 4 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f4 by tc4cr page 125 TMP86FS28FG clr (tc4cr).3: stops the timer. clr (tc4cr).7 : sets the pwm 4 pin to the high level. note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc, fc/2 or fs is select ed as the source clock, a pulse is output from the pwm 4 pin during the warm-up period time after exiting the stop mode. table 9-7 16-bit pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 [hz] fs/2 3 [hz] 128 p s244.14 p s 8.39 s 16 s fc/2 7 fc/2 7 ?8 p s ? 524.3 ms ? fc/2 5 fc/2 5 ?2 p s ? 131.1 ms ? fc/2 3 fc/2 3 ? 500 ns ? 32.8 ms ? fs fs fs 30.5 p s30.5 p s2 s 2 s fc/2 fc/2 ? 125 ns ? 8.2 ms ? fc fc ? 62.5 ns ? 4.1 ms ? example :generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 mhz) setting ports ldw (pwreg3), 07d0h : sets the pulse width. ld (tc3cr), 33h : sets the operating clock to fc/2 3 , and 16-bit pwm output mode (lower byte). ld (tc4cr), 056h : sets tff4 to the initial value 0, and 16-bit pwm signal generation mode (upper byte). ld (tc4cr), 05eh : starts the timer. page 126 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86FS28FG figure 9-7 16-bit pwm m ode timing chart (tc3 and tc4) 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc4cr page 127 TMP86FS28FG 9.3.8 16-bit programmable pulse generate (ppg) ou tput mode (tc3 and 4) this mode is used to generate pulses with up to 16- bits of resolution. the timer counter 3 and 4 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the inte rnal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4 ) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again when a match betw een the up-counter and th e timer register (ttreg3, ttreg4) value is detected, and the counter is cleared. the inttc4 interrupt is generated at this time. since the initial value can be set to the timer f/f4 by tc4cr page 128 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86FS28FG figure 9-8 16-bit ppg mode timing chart (tc3 and tc4) 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc4cr page 129 TMP86FS28FG 9.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 3 and 4 are cascadable to form a 16-bit timercounter. the warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. note 1: in the warm-up counter mode, fi x tcicr page 130 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86FS28FG 9.3.9.2 high-frequency warm-up counter mode (slow1 o slow2 o normal2 o normal1) in this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. before starting the timer, set sy scr2 page 131 TMP86FS28FG 10. 8-bit timercounter (tc5, tc6) 10.1 configuration figure 10-1 8-bit ti mercounter 5, 6 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc6cr tc5cr ttreg6 pwreg6 ttreg5 pwreg5 tc5 pin tc6 pin tc6s tc5s inttc5 interrupt request inttc6 interrupt request tff6 tff5 pdo 6/pwm 6/ ppg 6 pin pdo 5/pwm 5/ pin tc5ck tc6ck tc5m tc5s tff5 tc6m tc6s tff6 timer f/f6 timer f/f5 page 132 10. 8-bit timercounter (tc5, tc6) 10.1 configuration TMP86FS28FG 10.2 timercounter control the timercounter 5 is controlled by the timercounter 5 control register (tc5cr) and two 8-bit timer registers (ttreg5, pwreg5). note 1: do not change the timer register (t treg5) setting while the timer is running. note 2: do not change the timer register (pwreg5) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc5m, tc5ck and tff5 settings while the timer is running. note 3: to stop the timer operation (tc5s= 1 o 0), do not change the tc5m, tc5ck and tff5 settings. to start the timer opera- tion (tc5s= 0 o 1), tc5m, tc5ck and tff5 can be programmed. note 4: to use the timercounter in the 16-bit mode, set th e operating mode by programming tc6cr page 133 TMP86FS28FG note 7: the timer register settings are limited depending on t he timer operating mode. for the detailed descriptions, see table 10- 3. note 8: the operating clock fc in t he slow or sleep mode can be used only as the high-frequency warm-up mode. page 134 10. 8-bit timercounter (tc5, tc6) 10.1 configuration TMP86FS28FG the timercounter 6 is controlled by the timercounter 6 control register (tc6cr) and two 8-bit timer registers (ttreg6 and pwreg6). note 1: do not change the timer register (t treg6) setting while the timer is running. note 2: do not change the timer register (pwreg6) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc6m, tc6ck and tff6 settings while the timer is running. note 3: to stop the timer operation (tc6s= 1 o 0), do not change the tc6m, tc6ck and tff6 settings. to start the timer operation (tc6s= 0 o 1), tc6m, tc6ck and tff6 can be programmed. note 4: when tc6m= 1** (upper byte in the 16-bit mode), the sour ce clock becomes the tc5 over flow signal regardless of the tc6ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc6m, where tc5cr page 135 TMP86FS28FG note 6: to the timercounter in the 16-bit mode, select the so urce clock by programming tc5cr page 136 10. 8-bit timercounter (tc5, tc6) 10.1 configuration TMP86FS28FG note: n = 5 to 6 table 10-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 d (ttregn) d 255 8-bit pdo 1 d (ttregn) d 255 8-bit pwm 2 d (pwregn) d 254 16-bit timer/event counter 1 d (ttreg6, 5) d 65535 warm-up counter 256 d (ttreg6, 5) d 65535 16-bit pwm 2 d (pwreg6, 5) d 65534 16-bit ppg 1 d (pwreg6, 5) < (ttreg6, 5) d 65535 and (pwreg6, 5) + 1 < (ttreg6, 5) page 137 TMP86FS28FG 10.3 function the timercounter 5 and 6 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 5 and 6 (tc5, 6) are cascadable to form a 16- bit timer. the 16-bit timer has the operat ing modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 10.3.1 8-bit timer mode (tc5 and 6) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr page 138 10. 8-bit timercounter (tc5, tc6) 10.1 configuration TMP86FS28FG figure 10-2 8-bit timer mode timing chart (tc6) 10.3.2 8-bit event counter mode (tc5, 6) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj valu e is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr page 139 TMP86FS28FG note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediatel y after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr page 140 10. 8-bit timercounter (tc5, tc6) 10.1 configuration TMP86FS28FG figure 10-4 8-bi t pdo mode timing chart (tc6) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc6cr page 141 TMP86FS28FG 10.3.4 8-bit pulse width modulat ion (pwm) output mode (tc5, 6) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr page 142 10. 8-bit timercounter (tc5, tc6) 10.1 configuration TMP86FS28FG figure 10-5 8-bit pwm mode timing chart (tc6) 1 0 nn+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc6cr page 143 TMP86FS28FG 10.3.5 16-bit time r mode (tc5 and 6) in the timer mode, the up-counter counts up using the internal clock. the timercounter 5 and 6 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg5, ttreg6) valu e is detected after the timer is started by setting tc6cr page 144 10. 8-bit timercounter (tc5, tc6) 10.1 configuration TMP86FS28FG 10.3.6 16-bit event c ounter mode (tc5 and 6) 10.3.7 16-bit pulse wi dth modulation (pwm) ou tput mode (tc5 and 6) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 5 and 6 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg5, pwreg6) value is detected, the logic level output from the timer f/f6 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f6 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc6 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc5 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f6 by tc6cr |